A flip chip package includes a direct electrical connection of a down-facing (that is, “flipped”) semiconductor chip onto a substrate, such as a ceramic substrate or a circuit board, using conductive bumps. Flip chip technology is quickly replacing older wire bonding technology that uses up-facing chips with conductive wires to connect bond pads on chips to substrates.
FIG. 1 illustrates a cross-sectional view of a conventional flip-chip package, which includes semiconductor chip (also referred to as a die in the packaging art) 10 bonded onto package substrate 12 through solder bumps 14. Underfill 15 is filled between solder bumps 14 to protect solder bumps 14 from cracking. The backside of die 10 is thermally coupled to heat sink 18. Heat sink 18 may be secured onto printed circuit board (PCB) 20 through screws or spring clamps (not shown).
After the package as shown in FIG. 1 is formed, but before it is used, the force applied on die 10 only includes the weight of heat sink 18, and the force applied by the screws or spring clamps. During the usage of the package, however, the temperature of die 10 rises, which may reach as high as about 125° C. The stress applied on die 10 thus rises due to the mismatch between coefficients of thermal expansion (CTE) of die 10 and package substrate 12. Typically, the CTE of die 10 is about 3, while the CTE of package substrate 12 is about 15 to about 17. The significant CTE mismatch results in the increase of the stress applied on die 10, and will cause solder bumps 14 to crack.
Conventionally, the problem of the increased stress may be solved by applying stronger underfill 15. However, in recent generations of integrated formation technologies, low-k dielectric materials are increasingly used, and the k values of the low-k dielectric materials become increasingly lower. The strengths of the low-k dielectric materials are thus increasingly weaker. Unfortunately, stronger underfill 15 causes a greater stress to be applied on the low-k dielectric layers in die 10, resulting in the delamination of the low-k dielectric layers.
To protect the low-k dielectric layers, underfill 15 preferably has a low glass transition temperature (Tg). Low-Tg underfills become soft at relatively low temperatures. When the temperature of die 10 rises, the modulus of underfill 15 decreases, so that the stress applied on the low-k dielectric materials is released. However, with lower modulus, the protection provided by low-Tg underfill 15 to solder bumps 14 is reduced, subject solder bumps 14 to cracking, which may result in an open circuit. The conflicting requirements of solder bumps 14 and low-k dielectric materials hence require a new package structure, and methods for forming the same.